1. Field of the Invention
The present invention relates to reproduction of clock and data in high-speed transmission, and more particularly relates to a technology for transmitting signals between LSI chips, between a plurality of devices and circuit blocks in an LSI chip and, between boards and between cabinets at high speed.
2. Description of the Related Art
Today, in order to improve the performance of a system, the performance of components composing a computer and other information processing equipment, such as static random-access memory (SRAM), dynamic random-access memory (DRAM), a processor, a switching LSI and the like, is improved. In order to improve the performance of a system, using such a high-performance component, an LSI device or the like, signal transfer speed must be improved. Specifically, the increase of a data transfer rate measured by bit/second and transmission delay must be reduced.
For example, a speed gap at the time of transmission between memory, such as SRAM, DRAM or the like and a processor has a tendency to increase, and this speed gap disturbs the performance improvement of a computer. Besides the speed gap at the time of transmission, with a larger-scaled chip in an LSI, the signal transmission speed between a device and a circuit block in the chip is a big factor in restricting the performance of the chip.
Furthermore, the signal transmission speed must also be improved between servers or boards.
Conventionally, in order to realize signal transmission/reception at such a high data rate described above (to improve signal transmission speed), a clock must be generated in synchronization with data reception and data must be determined by the clock. In this case, although data determination generally means binary determination of one bit, n bit determination can also be possible.
Generally, a receiving clock is generated by a sort of phase feedback circuit, such as a phase tracking method or the like. FIG. 1A shows the phase tracking method. The phase tracking method circuit comprises a determination circuit (FF) 2201, a clock phase adjustment circuit 2202 and a phase detection circuit 2203. Data is inputted to the determination circuit 2201 and the phase detection circuit 2203, and the clock phase adjustment circuit 2202 reproduces a clock, based on the result of the phase detection. The reproduced clock is returned to the phase detection circuit 2203 and is used for subsequent clock phase adjustment. FIG. 1B shows such a binary determination waveform by a clock inputted to the determination circuit 2201. However, in the phase tracking method, although a clock with low jitters can be reproduced, the rapid fluctuation of a clock phase cannot be tracked.
In such a case, an over-sampling method with high tolerance against RF jitters included a clock can be used. In the over sampling method, decision is made at a rate sufficiently higher than a data rate, and one decided in an appropriate timing, of the results is selected later (decided and picked). Since the over-sampling does not include a feedback circuit for adjusting a clock phase, even a clock with high frequency jitters can be tracked.
FIG. 2A shows an over-sampling method circuit. The circuit comprises a determination circuit (FF) 2301, an over-sampling clock generation circuit 2302 and a data selection circuit 2303. The over-sampling determination circuit 2301 over-samples at a rate of approximately three to five times as much as a data rate. The clock generation circuit 2302 externally generates a reference clock for sampling data, using an external clock. The generated signal is transferred to the over-sampling determination circuit 2301. The data selection circuit 2303 selects and outputs data. FIG. 2B shows an over-sampling method binary determination waveform. Data is sampled by a plurality of clocks whose phases are shifted at equal intervals.
FIG. 3 shows another conventional over-sampling method circuit. The circuit comprises an over-sampling determination circuit 2401, a clock generation circuit 2402 and a data selection circuit 2403. The clock generation circuit 2402 externally obtains and generates a reference clock for sampling data, using an external clock. The generated signal is transferred to the over-sampling determination circuit 2401 and the data selection circuit 2403. The data selection circuit 2403 selects and outputs data. In this case, if the clock frequency of outputted data and the clock frequency of inputted data are not kept at an integral ratio, data overlaps or misses. Therefore, flow control is needed later.
In the over-sampling method disclosed by Japanese Patent Application Publication No. 2004-088386, skew correction is applied using a specific pattern signal. The edge of over-sampled data is statistically processed, the most stable edge is selected and appropriate data is reproduced by sampling data using the edge.
According to Japanese Patent Application Publication No. 2001-320353, no voltage controlled oscillator is used, and a phase control circuit and an analog delay-locked loop are used. The phase control circuit receives a fairly small number of clocks and controls the phases of a fairly small number of clocks. Then, the analog delay-locked loop develops the phase-controlled clocks up to number of phases needed for phase comparison. The clocks are supplied to a phase comparator. Thus, its jitter tolerance can be improved and a good clock can be generated.
According to Japanese Patent Application Publication No. H11-261409, the power consumption is reduced by stopping the useless operation in the locked state of an over-sampling method clock reproduction circuit. Japanese Patent Application Publication No. H10-313302 discloses phase control.
However, the over-sampling method and the clock/data reproduction circuit have the following problems. There is often a little difference between an internal clock frequency and the clock frequency of received data in signal transmission between devices and the like. In this case, in the over-sampling method, cyclical data overlap and missing occurs in data outputted from a receiving circuit. In order to cope with this, a sufficiently large buffer must be provided on the output side of the receiving circuit, and also flow control must be performed by a higher-order protocol. Such a flow control cannot be always realized by a communication protocol.